DESIGN AND IMPLEMENTATION OF PATTERN LATCHING ALGORITHM FOR MCU PERFORMANCE ANALYSIS USING RING OSCILLATOR
B.Mysura Reddy
, Ch.Prasanthi , B.Praveen Kumar , Sk.Faiz Ahamed
MCU validation, Pattern Latching Algorithm, PLA, Ring Oscillator, DDLL, FPGA, Machine Learning, Performance Monitoring
This paper proposes an innovative methodology for evaluating microcontroller unit (MCU) performance using a Pattern Latching Algorithm (PLA) combined with a Digital Delay Locked Loop (DDLL). This integration improves frequency stability, jitter control, and phase noise reduction. The approach enables dynamic adaptability and reduced power consumption, making it ideal for energy-constrained embedded systems. Furthermore, we explore FPGA implementation and outline future extensions involving machine learning-based predictive analytics for robust performance monitoring.
"DESIGN AND IMPLEMENTATION OF PATTERN LATCHING ALGORITHM FOR MCU PERFORMANCE ANALYSIS USING RING OSCILLATOR", TIJER - TIJER - INTERNATIONAL RESEARCH JOURNAL (www.TIJER.org), ISSN:2349-9249, Vol.12, Issue 4, page no.a517-a523, April-2025, Available :https://tijer.org/TIJER/papers/TIJER2504075.pdf
Volume 12
Issue 4,
April-2025
Pages : a517-a523
Paper Reg. ID: TIJER_157436
Published Paper Id: TIJER2504075
Downloads: 000309
Research Area: Science and Technology
Country: Triupati , Andhra Pradesh, India
DOI: http://doi.one/10.1729/Journal.44767
ISSN: 2349-9249 | IMPACT FACTOR: 8.57 Calculated By Google Scholar | ESTD YEAR: 2014
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 8.57 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: TIJER (IJ Publication) Janvi Wave
